1. Field of the Invention
The present invention relates to electrostatic discharge protection devices, and in particular relates to electrostatic discharge protection device structures and layouts.
2. Description of the Related Art
An electrostatic discharge (ESD) event happens when electrostatic charges move from one surface to another. In VLSI circuits, electrostatic current may cause damage to semiconductor junctions, metal parts, and gate structures. FIG. 1 shows a conventional ESD protection device. In FIG. 1, a zener diode Z1 serves as a conventional ESD protection device for protecting a circuit C1. The cathode of the zener diode Z1 is connected to an input/output I/O of the circuit C1, and the anode of the zener diode Z1 is connected to a reference node VSS of the circuit C1. When an electrostatic discharge (ESD) event occurs at the input/output I/O, a high voltage potential larger than a junction breakdown voltage of the zener diode Z1 sets the zener diode Z1 to forward biased, and creates a current path dissipating ESD charges to the reference node VSS.
However, with the advancement of semiconductor fabrication technology, the breakdown voltages of sub-80 nm gate dielectrics are close to or less than 3˜4 V, and the trigger voltage of a conventional zener diode is around 9V. As a result, an ESD event can occur and damage the gate dielectrics of the VLSI circuit before the activation of the zener diode. A novel ESD protection device with a lower trigger voltage and lower holding voltage is desired.